This invention relates to the molding and application of protective caps to microelectronic semiconductor chips on a wafer scale as opposed to application on an individual chip basis. More particularly the invention relates to the molding and application of protective caps to semiconductor chips incorporating Micro Electro Mechanical Systems (MEMS). However the invention is not limited to MEMS applications.
Semiconductor chips are normally packaged in a protective layer or layers to protect the chip and its wire bonds from atmospheric and mechanical damage. Existing packaging systems typically use epoxy molding and thermal curing to create a solid protective layer around the chip. This is normally carried out on individually diced chips bonded to lead frames and so must be done many times for each wafer. Alternative methods of packaging include hermetically sealed metal or ceramic packages, and array packages such as ball grid array (BGA) and pin grid array (PGA) packages. Recently wafer scale packaging (WSP) has started to be used. This is carried out at the wafer stage before the chips are separated. The use of molding and curing techniques subjects the wafer to both mechanical and thermal stresses. In addition the protective cap so formed is a solid piece of material and so cannot be used for MEMS devices, since the MEMS device would be rendered inoperable by the polymer material. Existing packaging systems for MEMS devices include thematically sealed packages for individual devices, or use silicon or glass wafer scale packaging, both of which are relatively high cost operation.
In one broad form the invention provides a package including:
a) a chip having a top surface and a bottom surface and having at least one micro fabricated device formed in or on the chip, and
b) a first molded hollow cap bonded to the top surface which, in plan view, overlays part or all of said at least one device,
wherein the first cap has been bonded to the chip at the wafer stage prior to separation of the wafer into individual packages.
The bond pads are preferably formed on or in the top surface but may be formed on or in the bottom surface.
The package may further include a second molded cap bonded to the bottom surface of the chip. The second cap may, in plan view, overlay part or all of the at least one device.
The devices may each be an ink jet device, an accelerometer, a light emitting device, a laser, other MEMS or MOEMS devices or other micro electrical or electromechanical devices or other micro-fabricated devices.
The first cap may include a portion substantially transparent to electromagnetic radiation at one or more wavelengths.
The first cap may include one or more portions capable of refracting electromagnetic radiation passing therethrough.
The first cap may include one or more apertures in a central portion.
In another broad form the invention provides an ink jet print head package including:
a chip having a top surface and a bottom surface and having at least one ink ejection device located on or adjacent to the top surface;
a first hollow molded cap bonded to the top surface and which, in plan view, overlays part or all of the at least one ink ejection device; and
wherein the first cap has been bonded to the chip at the wafer stage prior to separation of the wafer into individual packages.
The first cap of the ink jet print head package may have an aperture in a central portion for each ink ejection device or group of ink ejection devices and aligned to allow ink ejected by a respective ink ejection device to escape to the environment.
The inkjet print head package may further include one or more ink supply apertures extending through the chip to communicate the one or more the ink ejection devices with the second surface.
The ink jet print head package may further include a second hollow cap bonded to the bottom surface of the chip at the wafer stage to define a second cavity. The second cap may, in plan view, overlay part or all of the one or more ink jet ejection devices. The second cap may have at least one aperture to communicate the second cavity with the outside environment.
Each second cap may have one or more walls extending from the central portion to bond with the chip to divide the second cavity into two or more channels. The second cap may have one or more apertures extending through the central portion to communicate a respective channel with the outside environment.
The chip may have one or more slots or apertures extending through the thickness of the chip to communicate the devices with the channels. There may be one slot for each channel or there may be multiple slots per channel.